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PSD211R ZPSD211R, ZPSD211RV
Low Cost Field Programmable Microcontroller Peripherals
FEATURES SUMMARY s Single Supply Voltage: - 5 V10% for PSD211R and ZPSD211R - 2.7 to 5.5 V for ZPSD211RV
s s s s
Figure 1. Packages
Up to 256 Kbit of EPROM Input Latches Programmable I/O ports Programmable Security
PLDCC44 (J) CLDCC44 (L) PQFP44 (M)
January 2002
1/3
PSD211R Family
PSD211R ZPSD211R ZPSD211RV Low Cost Microcontroller Peripherals Table of Contents
1 2 3 4 5 6 7 8 9 10 Introduction ...........................................................................................................................................................1 Notation ................................................................................................................................................................2 Key Features ........................................................................................................................................................4 PSD211R Family Feature Summary ....................................................................................................................5 Partial Listing of Microcontrollers Supported ........................................................................................................5 Applications ..........................................................................................................................................................5 ZPSD Background ................................................................................................................................................5 7.1 Integrated Power ManagementTM Operation .............................................................................................6 Operating Mode ....................................................................................................................................................9 Programmable Address Decoder (PAD)...............................................................................................................9 I/O Port Functions ...............................................................................................................................................12 10.1 CSIOPORT Registers..............................................................................................................................12 10.2 Port A (PA0-PA7).....................................................................................................................................12 10.3 Port B (PB0-PB7).....................................................................................................................................14 10.4 Port C (PC0-PC2) ....................................................................................................................................15 PSD Memory ......................................................................................................................................................16 11.1 EPROM....................................................................................................................................................16 11.2 Programming and Erasure.......................................................................................................................16 Control Signals ...................................................................................................................................................16 12.1 ALE or AS ................................................................................................................................................17 12.2 WR or R/W...............................................................................................................................................17 12.3 RD/E ........................................................................................................................................................17 12.4 PSEN .......................................................................................................................................................17 12.5 A19/CSI ...................................................................................................................................................17 12.6 Reset Input ..............................................................................................................................................18 Program/Data Space and the 8031 ....................................................................................................................20 Systems Applications..........................................................................................................................................21 Security Mode .....................................................................................................................................................23 Power Management............................................................................................................................................23 16.1 CSI Input..................................................................................................................................................23 16.2 CMiser Bit ................................................................................................................................................23 16.3 Turbo Bit (ZPSD Only).............................................................................................................................24 16.4 Number of Product Terms in the PAD Logic............................................................................................24 16.5 Composite Frequency of the Input Signals to the PAD Logic..................................................................25 16.6 Loading on I/O Pins .................................................................................................................................26 Calculating Power ...............................................................................................................................................27 Specifications......................................................................................................................................................30 18.1 Absolute Maximum Ratings .....................................................................................................................30 18.2 Operating RAnge .....................................................................................................................................30 18.3 Recommended Operating Conditions......................................................................................................30 18.4 Pin Capacitance.......................................................................................................................................30 18.5 AC/DC Characteristics - PSD211R/ZPSD211R (All 5 V devices)...........................................................31 18.6 AC/DC Characteristics - PSD211RV (3 V devices only).........................................................................32 18.7 Timing Parameters - PSD211R/ZPSD211R (All 5 V devices) ................................................................33 18.8 Timing Parameters - ZPSD211RV (3 V devices only) ............................................................................34 18.9 Timing Diagrams for PSD211R Parts .....................................................................................................36 18.10 AC Testing ...............................................................................................................................................39
11
12
13 14 15 16
17 18
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PSD211R Family
PSD211R ZPSD211R ZPSD211RV Low Cost Microcontroller Peripherals Table of Contents
19 20 21 22
(cont.)
23
Pin Assignments .................................................................................................................................................40 Package Information ...........................................................................................................................................41 Package Drawings ..............................................................................................................................................42 PSD211R Ordering Information ..........................................................................................................................45 22.1 Selector Guide .........................................................................................................................................45 22.2 Part Number Construction .......................................................................................................................46 22.3 Ordering Information................................................................................................................................46 Data Sheet Revision History ...............................................................................................................................47 Sales Reps .........................................................................................................................................................48
ii
Programmable Peripheral
PSD211R
Field-Programmable Microcontroller Peripheral
1.0 Introduction
The low cost PSD211R family integrates high-performance and user-configurable blocks of EPROM and programmable logic into one part. The PSD211R products also provide a powerful microcontroller interface that eliminates the need for external "glue logic". The part's integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. The major functional blocks of the PSD211R include: * Two programmable logic arrays * 256 Kb of EPROM * Input latches * Programmable I/O ports * Programmable security
The PSD211R family architecture (Figure 1) can efficiently interface with, and enhance, almost any 8-bit multiplexed microcontroller system. This solution provides microcontrollers the following: * Chip-select logic, control logic, and latched address signals that are otherwise implemented discretely * Port expansion (reconstructs lost microcontroller I/O) * An EPROM (with security) * Compatible with 8031-type architectures that use separate Program and Data Space.
Updated March 1, 1999. See page 47.
1
PSD211R Family
1.0 Introduction
(Cont.)
The PSD211R I/O ports can be used for: * Standard I/O ports * Programmable chip select outputs * Address inputs * Demultiplexed address outputs. Implementing your design has never been easier than with PSDsoft--WSI's software development suite. Using PSDsoft, you can do the following: * Configure your PSD211R to work with virtually any 8-bit microcontroller * Specify what you want implemented in the programmable logic using a high-level Hardware Description Language (HDL) * Simulate your design * Download your design to the part using a programmer.
2.0 Notation
Throughout this data sheet, references are made to the PSD211R. In most cases, these references also cover the ZPSD211R and ZPSD211RV products. Exceptions will be noted. Also, references to the ZPSD211R will also cover the low-voltage ZPSD211RV. (Again, exceptions will be noted.) Use the following table to determine what references cover which product versions:
Reference
PSD211R or PSD PSD211R only Non-ZPSD ZPSD versions only Non-V versions V versions only or 3 V part only or ZPSD211RV only
PSD211R
X X X
ZPSD211R
X
ZPSD211RV
X
X X X
X
X
2
PSD211R Family
Figure 1. PSD211R Family Architecture
A8-A15 L A T C H
A11-A15 A8-A10 A16-A18 LOGIC IN A19/CSI ALE/AS RD WR RESET ALE/AS CS8-CS10 CS0-CS7 ES7 ES6 ES5 ES4 ES3 ES2 ES1 ES0 EPROM 256Kb PORT B 13 P.T. PAD A A19/CSI ALE/AS RD WR RESET PORT C 27 P.T. PAD B PROG. PORT EXP.
PC0-PC2
AD0-AD7
L A T C H
PROG. PORT EXP.
PB0-PB7
D0-D7 CSIOPORT
PROG. PORT EXP. ALE/AS A0-A7 PA0-PA7
RD/E WR/R/W PSEN RESET A19/CSI PROG. CONTROL SIGNALS
PORT A
PROG. CHIP CONFIGURATION
3
PSD211R Family
3.0 Key Features
t Low cost programmable microcontroller peripheral t 256Kb of UV EPROM with the following features:
* * * * * *
Configurable as 32 K x 8 Divided into eight equally-sized mappable blocks for optimized address mapping As fast as 70 ns access time, which includes address decoding
t 19 I/O pins that can be individually configured for :
Microcontroller I/O port expansion Programmable Address decoder (PAD) I/O Latched address output
t Two Programmable Arrays (PAD A and PAD B) replace your discrete PLD or decoder
and have the following features: * Up to 13 Inputs and 24 outputs * 36 Product terms (9 for PAD A and 27 for PAD B) * Ability to decode up to 1 MB of address
t Microcontroller logic that eliminates the need for external "glue logic" has the following
features: * Ability to interface to multiplexed buses * Built-in address latches for multiplexed address/data bus * ALE and Reset polarity are programmable (Reset polarity not programmable on V-versions) * Multiple configurations are possible for interface to many different microcontrollers
t Programmable power management with standby current as low as 1A
(V versions only) * CMiser bit--programmable option to reduce AC power consumption in memory * Turbo Bit (ZPSD only)--programmable bit to reduce AC and DC power consumption in the PADs
t Built-in security locks the device and PAD decoding configuration t Wide Operating Voltage Range
* *
V-versions: 2.7 to 5.5 volts Others: 4.5 to 5.5 volts
t Available in a variety of packaging (44-pin PLDCC, CLDCC, and PQFP) t Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.
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PSD211R Family
4.0 PSD211R Family Feature Summary
Use the following table to determine which PSD product will fit your needs. Refer back to this page whenever there is confusion as to which part has what features.
Table 1. PSD211R Product Summary # PLD Inputs
13 13 13
Part
PSD211R ZPSD211R ZPSD211RV
EPROM Size
256 Kb 256 Kb 256 Kb
Voltage
5V 5V 3 V/5 V
Turbo Bit
X X
Typical Standby Current
50 A 10 A 1 A
NOTE: The low power version of the ZPSD211R (the ZPSD211RV) can only accept an active-low level Reset input.
5.0 Partial Listing of Microcontrollers Supported
t Motorola family: 68HC11, 68HC05C0 t Intel family: t Philips family: t Zilog:
80C31, 80C51, 80C188, 80C198 80C31 and 80C51 based MCUs Z8
6.0 Applications
t Telecommunications:
* * * * * * * * * * * *
Cellular phone Digital PBX Digital speech FAX Digital Signal Processing (DSP) Industrial Control Measurement meters Data recorders Security and access control Hearing aids Monitoring equipment Diagnostic tools
t Portable Industrial Equipment:
t Medical Instrumentation:
7.0 ZPSD Background
Portable and battery-powered systems have recently become major embedded control application segments. As a result, the demand for electronic components having extremely low power consumption has increased dramatically. Recognizing this trend, WSI, Inc. developed a new lower power PSD part, denoted ZPSD211R. The Z stands for Zero-power because ZPSD products virtually eliminate the DC component of power consumption, reducing it to standby levels. Virtual elimination of the DC component is the basis for the words "Zero-power" in the ZPSD name. ZPSD products also minimize the AC power component when the chip is changing states. The result is a programmable microcontroller peripheral family that replaces discrete circuit components, while drawing less power.
5
PSD211R Family
7.0 ZPSD Background
(Cont.)
7.1 Integrated Power Management TM Operation
Upon each address or logic input change to the ZPSD, the device powers up from low power standby for a short time. Then the ZPSD consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. After the new outputs are stable, the ZPSD latches them and automatically reverts back to standby mode. The ICC current flowing during standby mode and during DC operation is identical and is only a few microamperes. The ZPSD automatically reduces its DC current drain to these low levels and does not require controlling by the CSI (Chip Select Input). Disabling the CSI pin unconditionally forces the ZPSD to standby mode independent of other input transitions. The only significant power consumption in the ZPSD occurs during AC operation. The ZPSD contains the first architecture to apply Zero-power techniques to memory and logic blocks. Figure 2 compares ZPSD zero power operation to the operation of a discrete solution. A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and the generation of an address. The ZPSD detects the address transition and powers up for a short time. The ZPSD then latches the outputs of the PAD and EPROM to the new values. After finishing these operations, the ZPSD shuts off its internal power, entering standby mode. The time taken for the entire cycle is less than the ZPSD's "access time." The ZPSD will stay in standby mode while its inputs are not changing between bus cycles. In an alternate system implementation using discrete EPROM, and other discrete components, the system will consume operating power during the entire bus cycle. This is because the chip select inputs on the memory devices are usually active throughout the entire cycle. The AC power consumption of the ZPSD may be calculated using the composite frequency of the MCU address and control signals, as well as any other logic inputs to the ZPSD.
Figure 2. ZPSD Power Operation vs. Discrete Implementation
ALE
ADDRESS
EPROM ACCESS
EPROM ACCESS
EPROM ACCESS
DISCRETE EPROM & LOGIC
ICC ZPSD ZPSD ZPSD
TIME
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PSD211R Family
Table 2. PSD211R Pin Descriptions
Name
Type
Description
This pin is for 8031 or compatible MCUs that use PSEN to separate program space from data space. In this case, PSEN is used for reads from the EPROM. Notes: 1) If your MCU does not output a PSEN signal, pull up this pin to VCC. 2) In programming mode, this pin is pulsed between VPP and 0 V. The following control signals can be connected to this port, based on your MCU (and the way you configure the PSD in PSDsoft): 1. WR--active-low write pulse. 2. R/W--active-high read/active-low write input. Note: in programming mode, this pin must be tied to VPP. The following control signals can be connected to this port, based on your MCU (and the way you configure the PSD in PSDsoft): 1. RD--active-low read input. 2. E--E clock input. The following control signals can be connected to this port: 1. CSI-Active-low chip select input. If your MCU supports a chip select output, and you want the PSD to save power when not selected, use this pin as a chip select input. 2. If you don't wish to use the CSI feature, you may use this pin as an additional input (logic or address) to the PAD. A19 can be latched with ALE/AS, or be a transparent logic input. PSD211R/ZPSD211R: This pin is user-programmable and can be configured to reset on a high- or low-level input. Reset must be applied for at least 100 ns.
PSEN
I
WR/VPP or R/W/VPP
I
RD/E
I
A19/CSI
I
Reset
I
ZPSD211RV: This pin is not configurable, and the chip will only reset on an active-low level input. Reset must be applied for at least 500 ns, and no operations may take place for an additional 500 ns minimum. (See Figure 8.) Connect ALE or AS to this pin. The polarity of this pin is configurable. The trailing edge of ALE/AS latches all multiplexed address inputs.
ALE/AS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
I
I/O
These pins make up Port A. These port pins are configurable, and can have the following functions: (see Figure 5) 1. MCU I/O--in this mode, the direction of the pin is defined by its direction bit, which resides in the direction register. 2. Latched address output.
I/O
These pins make up Port B. These port pins are configurable, and can have the following functions: (see Figure 6) 1. MCU I/O --in this mode, the direction of the pin is defined by its direction bit, which resides in the direction register. 2. Chip select output --each of PB0-3 has four product terms available per pin, while PB4-7 have 2 product terms each. See Figure 4.
Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power.
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PSD211R Family
Table 1. PSD211R Pin Descriptions
(cont.)
Name
Type
Description
These pins make up Port C. These port pins are configurable, and can have the following functions (see Figure 7): 1. PAD input--when configured as an input, a bit individually becomes an address or a logic input, depending on your PSDsoft design file. When declared as an address, the bits are latched with ALE/AS. 2. PAD output--when configured as an output (i.e. there is an equation written for it in your PSDsoft design file), there is one product term available to it.
PC0 PC1 PC2
I/O
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 GND VCC
I/O
These pins are the multiplexed, low-order address/data byte (AD0-AD7). As inputs, address information is latched by the ALE/AS signal and used internally by the PSD. The pins also serve as MCU data bus inputs or outputs, depending on the MCU control signals (RD, WR, etc.).
I/O
These pins are the high-order address inputs (A8-A15).
P P
Ground Pin Supply voltage input.
Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power.
8
PSD211R Family
8.0 Operating Mode
The PSD211R operates in 8-bit address/data mode, enabling it to interface directly to a variety of 8-bit multiplexed microcontrollers. It works as follows: the address/data bus (AD0-AD7) is bi-directional and permits the latching of the address when the ALE/AS signal is active. On the same pins, the data is read from or written to the device, depending on the state of the control signals (WR, RD, etc.). You should connect your MCU according to the following figure. Ports A through C can be configured according to Table 3, below.
Figure 3. Connecting a PSD211R to an 8-Bit Multiplexed-Bus MCU
Your 8-bit MCU
AD0 -AD7 A8 -A15 ALE/AS PSEN R/ W or WR RD/E A19 / CSI RESET A16-A181
PA PSD211R PB PC
I /O or A0-A7 I /O or CS0-CS7 CS8 -CS10 OR
NOTE: 1. Connect A16-A18 to Port C if your MCU outputs more than 16 bits of address.
Table 3. Bus and Port Configuration Options Port
A B C
Configurations
I/O or low-order (latched) address lines I/O and/or CS0-CS7 A16-A18 or CS8-CS10
9.0 Programmable Address Decoder (PAD)
The PSD211R contains two programmable arrays, referred to as PAD A and PAD B (Figure 4). PAD A is used to generate chip select signals derived from the input address to the internal EPROM blocks and I/O ports. PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the decoding to select external devices or as a random logic replacement. PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft based on the designer's input. The PAD's non-volatile configuration is stored in a re-programmable CMOS EPROM. Windowed packages are available for erasure by the user. See Table 4 for a list of PAD A and PAD B functions.
9
PSD211R Family
Programmable Address Decoder (PAD)
Figure 4. PAD Description
ES0 ES1 ES2 ES3 ES4 ES5 ES6 ES7 RD/E CSIOPORT WR or R/W I/O BASE ADDRESS 8 EPROM BLOCK SELECT LINES
ALE or AS
PAD A
A19 CS0/PB0 A18 CS1/PB1 A17 CS2/PB2
A16
A15
CS3/PB3
CS4/PB4 A14 CS5/PB5 A13 CS6/PB6 A12 CS7/PB7
PAD B
A11
CS8/PC0 CSI CS9/PC1 RESET CS10/PC2
NOTES: 1. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs become non-active. See Tables 7A and 7B. 2. RESET deselects all PAD output signals. See Tables 8A and 8B. 3. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively. Either A18 or CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of Port C. Port C can be configured as either input or output.
10
PSD211R Family
Programmable Address Decoder (PAD)
(cont.)
Table 4. PSD211R PAD A and PAD B Functions Function
PAD A and PAD B Inputs
A19/CSI A16-A18 A11-A15 RD/E WR or R/W ALE/AS RESET In CSI mode (when high), PAD deselects all of its outputs and enters a power-down mode (see Tables 7A and 7B). In A19 mode, it is another input to the PAD. These are general purpose inputs from Port C. See Figure 4, Note 3. These are address inputs. This is the read pulse or enable strobe input. This is the write pulse or R/W select signal. This is the ALE or AS input to the chip. This deselects all outputs from the PAD; it can not be used in product term equations. See Tables 8A and 8B.
PAD A Outputs
ES0-ES7 These are internal chip-selects to the 8 EPROM banks. Each bank can be located on any boundary that is a function of one product term of the PAD address inputs. This internal chip-select selects the I/O ports. It can be placed on any boundary that is a function of one product term of the PAD inputs. See Table 5.
CSIOPORT
PAD B Outputs
CS0-CS3 CS4 -CS7 CS8-CS10 These chip-select outputs can be routed through Port B. Each of them is a function of up to four product terms of the PAD inputs. These chip-select outputs can be routed through Port B. Each of them is a function of up to two product terms of the PAD inputs. These chip-select outputs can be routed through Port C. See Figure 4, Note 3. Each of them is a function of one product term of the PAD inputs.
11
PSD211R Family
10.0 I/O Port Functions
The PSD211R has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications. The next section describes the control registers for the ports. Following that are sections that describe each port. Figures 5 through 7 show the structure of Ports A through C, respectively. Note: any unused inputs should be connected directly to ground or pulled up to VCC (using a 10K to 100K resistor).
10.1 CSIOPORT Registers
Control of the ports is primarily handled through the CSIOPORT registers. There are 24 bytes in the address space, starting at the base address labeled CSIOPORT. Since the PSD211R uses internal address lines A15-A11 for decoding, the CSIOPORT space will occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to reduce wasted address space by connecting lower order address lines (A10 and below) to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The CSIOPORT space must be defined in your PSDsoft design file. The following tables list the registers located in the CSIOPORT space.
Table 5. CSIOPORT Registers for 8-Bit Data Busses Offset (in hex) from CSIOPORT Base Address
+2 +4 +6 +3 +5 +7 +10
Register Name
Port A Pin Register Port A Direction Register Port A Data Register Port B Pin Register Port B Direction Register Port B Data Register Power Management Register (Note 1)
NOTE: 1. ZPSD only.
Type of Access Allowed
Read Read/Write Read/Write Read Read/Write Read/Write Read/Write
10.2 Port A (PA0-PA7) MCU I/O Mode
The default configuration of Port A is MCU I/O. In this mode, every pin can be set (at run-time) as an input or output by writing to the respective pin's direction flip-flop (DIR FF, Figure 5). As an output, the pin level can be controlled by writing to the respective pin's data flip-flop (DFF, Figure 5A). The Pin Register can be read to determine logic level of the pin. The contents of the pin register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin.
12
PSD211R
10.0 I/O Port Functions
(Cont.)
10.2 Port A (PA0-PA7) (Cont.) Latched Address Output Mode
Alternatively, any bit(s) of Port A can be configured to output a low-order demultiplexed address bus bit. The address is provided by the internal PSD address latch, which latches the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed address bits. This feature can eliminate the need for an external latch (for example: 74LS373) if you have devices that require low-order latched address bits. Although any pin of Port A may output an address signal, the pin is position-dependent. In other words, pin PA0 of Port A may only pass A0, PA1 only A1, and so on. The control registers of Port A are located in CSIOPORT space; see Table 5. Each pin of Port A can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port A do:
Register Name
Port A Pin Register Port A Direction Register Port A Data Register
0 Value
Sampled logic level at pin = `0' Pin is configured as input Data in DFF = `0'
1 Value
Sampled logic level at pin = `1' Pin is configured as output Data in DFF = `1'
Default Value
(Note 1)
X 0 0
NOTE: 1. Default value is the value after reset.
Figure 5. Port A Pin Structure
I N T E R N A L A D D R / D A T A B U S A D 0 / A D 7 RESET READ PIN
READ DATA
WRITE DATA
CK DFF D R
MCU I/O OUT
PORT A PIN
ENABLE ALE LATCHED ADDR OUT LATCH D R MUX
G
READ DIR
D WRITE DIR CK
DIR FF R
CONTROL
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PSD211R Family
10.0 I/O Port Functions
(Cont.)
10.3 Port B (PB0-PB7) MCU I/O Mode
The default configuration of Port B is MCU I/O. In this mode, every pin can be set (at run-time) as an input or output by writing to the respective pin's direction flip-flop (DIR FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin's data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the pin. The contents of the Pin Register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin.
Chip Select Output
Alternatively, each bit of Port B can be configured to provide a chip-select output signal from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is not limited to chip selects only; they can be used for generic combinatorial logic as well. Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7 signals is comprised of two product terms. The control registers of Port B are located in CSIOPORT space; see Table 5. Each pin of Port B can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port B do:
Register Name
Port B Pin Register Port B Direction Register Port B Data Register
0 Value
Sampled logic level at pin = `0' Pin is configured as input Data in DFF = `0'
1 Value
Sampled logic level at pin = `1' Pin is configured as output Data in DFF = `1'
Default Value
(Note 1)
X 0 0
NOTE: 1. Default value is the value after reset.
Figure 6. Port B Pin Structure
READ PIN I N T E R N A L C S O U T B U S I N T E R N A L D A T A B U S READ DIR
READ DATA
WRITE DATA
CK DFF D R
MCU I/O OUT
PORT B PIN
ENABLE MUX
CSn
C S 0
D 8
* * *
7
* * *
D 1 5 RESET WRITE DIR
D DIR CK FF R CONTROL
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PSD211R Family
10.0 I/O Port Functions
(Cont.)
10.4 Port C (PC0-PC2)
Each pin of Port C (Figure 7) can be configured as an input to PAD A and PAD B, or as an output from PAD B. As inputs, the pins are referenced as A16-A18. Although the pins are given this reference, they can be used for any address or logic input. [For example, A8-A10 could be connected to those pins to improve the resolution (boundaries) of CS0-CS7 to 256 bytes.] How they are defined in the PSDsoft design file determines: * Whether they are address or logic inputs * Whether the input is transparent or latched by the trailing edge of ALE/AS. Notes: 1) If the inputs are addresses, they are routed to PAD A and B, and can be used in any or all PAD equations. 2) If the inputs are logic, they are routed to PAD B and can be used for Boolean equations that are implemented in any or all of the CS0-CS10 PAD B outputs. 3) If Port C pins are configured as inputs, they can not be individually configured as address or logic and latched or transparent. They must be configured as a group to be address or logic and latched or transparent. Alternately, PC0-PC2 can become CS8-CS10 outputs, respectively, providing the user with more external chip-select PAD outputs. Each of the signals (CS8-CS10) is comprised of one product term.
Figure 7. Port C (PC0-PC2) Pin Structure
CS8 / CS9 / C S10 From PAD Latched Address Input A16/A17/A18 To PAD Logic Input Address In or Chip Select Out Port C I/O1 (PC0/PC1/PC2) D E M U X PSDsoft 2
Q
D En ALE
Input or Output Set by PSDsoft 2
NOTES: 1. Port C pins can be individually configured as inputs or outputs, but not both. 2. PSDsoft sets this configuration prior to run-time based on your PSDsoft design file.
15
PSD211R Family
11.0 PSD Memory
The following sections explain the EPROM memory block and how to program and erase the PSD211R.
11.1 EPROM
For all PSD211R devices, the EPROM is built using Zero-power technology. This means that the EPROM powers up only when the address changes. It consumes power for the necessary time to latch data on its outputs. After this, it powers down and remains in standby mode until the next address change. This happens automatically, and the designer has to do nothing special. The 32K x 8 EPROM is divided into eight equal-sized banks. Each bank can be placed in any address location by programming the PAD. Bank0-Bank7 are selected by PAD A outputs ES0-ES7, respectively. There is one product term for each bank select (ESi).
11.2 Programming and Erasure
Programming the device can be done using the following methods: * WSI's main programmer--PSDpro--which is accessible through a parallel port. * WSI's programmer used specifically with the PSD211R--PEP300. * WSI's discontinued programmer--Magic Pro. * A 3rd party programmer, such as Data I/O. Information for programming the device is available directly from WSI. Please contact your local sales representative. Also, check our web site (waferscale.com) for information related to 3rd party programmers. Upon delivery from WSI, or after each erasure (using windowed part), the PSD211R device has all bits in the PAD and EPROM in the HI state (logic 1). The configuration bits are in the LO state (logic 0). To clear all locations of their programmed contents (assuming you have a windowed version), expose the windowed device to an Ultra-Violet (UV) light source. A dosage of 30 W second/cm2 is required for PSD211R devices, and 40 W second/cm2 for low-voltage (V suffix) devices. This dosage can be obtained with exposure to a wavelength of 2537 A and intensity of 12000 W/cm2 for 40 to 45 minutes for the PSD211R and 55 to 60 minutes for the low-voltage (V suffix) devices. The device should be approximately 1 inch (2.54 cm) from the source, and all filters should be removed from the UV light source prior to erasure. The PSD211R devices will erase with light sources having wavelengths shorter than 4000 A. However, the erasure times will be much longer than when using the recommended 2537 A wavelength. Note: exposure to sunlight will eventually erase the device. If used in such an environment, the package window should be covered with an opaque substance.
12.0 Control Signals
Consult your MCU data sheet to determine which control signals your MCU generates, and how they operate. This section is intended to show which control signals should be connected to what pins on the PSD211R. You will then use PSDsoft to configure the PSD211R, based on the combination of control signals that your MCU outputs, for example RD, WR, and PSEN. The PSD211R is compatible with the following control signals: * ALE or AS (polarity is programmable) * WR or R/W * RD/E * PSEN * A19/CSI * RESET (polarity is programmable except on low voltage versions with the V suffix).
16
PSD211R Family
12.0 Control Signals
(Cont.)
12.1 ALE or AS
Connect the ALE or AS signal from your MCU to this pin where applicable, and program the polarity using PSDsoft. The trailing edge (when the signal goes inactive) of ALE or AS latches the address on the appropriate address pins.
12.2 WR or R/W
Your MCU should output a stand-alone write signal (WR) or a multiplexed read/write signal (R/W). In either case, the signal should be connected to this pin.
12.3 RD/E
Your MCU should output either RD or E (clock). In either case, connect the appropriate signal to this pin. Note: if you have an MCU that outputs DS, it will not be compatible with the PSD211R, and you must use a PSD3XX family device.
12.4 PSEN t If your MCU does not output PSEN (or some program select enable equivalent signal),
tie this pin to Vcc (through a series resistor), and skip to the next signal.
t If you use an 8-bit 8031 compatible MCU that outputs a separate signal when
accessing program space, such as PSEN, connect it to this pin. You would then use PSDsoft to configure the EPROM in the PSD211R to respond to PSEN only or PSEN and RD. If you have an 8031 compatible MCU, refer to the "Program/Data Space and the 8031" section for further information.
12.5 A19/CSI
This pin is configured using PSDsoft to be either a chip select for the entire PSD device or an additional PAD input. If your MCU can generate a chip-select signal, and you wish to save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic input.
t When configured as CSI (active-low PSD chip select): a low on this pin keeps the
PSD in normal operation. However, when a high is detected on the pin, the PSD enters Power-down Mode. See Tables 7A and 7B for information on signal states during Power-down Mode. See section 16 for details about the reduction of power consumption.
t When configured as A19, the pin can be used as an additional input to the PADs.
It can be used for address or logic. It can also be ALE/AS dependent or a transparent input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always enabled.
Table 7A. Signal States During Power-down Mode Port
AD0-AD15 Port Pins PA0-PA7 All MCU I/O Latched Address Out MCU I/O Port Pins PB0-PB7 Chip Select Outputs, CS0-CS7, CMOS Chip Select Outputs, CS0-CS7, Open Drain Port Pins PC0-PC2 Address or Logic Inputs, A16-A18 Chip Select Outputs, CS8-CS10, CMOS only
Configuration Mode(s)
State
Input (Hi-Z) Unchanged Logic 1 Unchanged Logic 1 Hi-Z Input (Hi-Z) Logic 1
17
PSD211R Family
12.0 Control Signals
(Cont.)
Table 7B. Internal States During Power-down Component
PAD A and PAD B All registers in CSIOPORT address space, including: Direction Data PMR (turbo bit, ZPSD only)
NOTE: N/A = Not Applicable
Internal Signal
CS0-CS10 CSIOPORT, ES0-ES7 N/A
Internal Signal State During Power-Down
Logic 1 (inactive) Logic 0 (inactive)
All unchanged
12.6 Reset Input
This is an asynchronous input to initialize the PSD device. Refer to tables 8A and 8B for information on device status during and after reset. The standard-voltage PSD211R and ZPSD211R (non-V) devices require a reset input. In this case, the reset input must be asserted for at least 100 nsec. The PSD will be functional immediately after reset is de-asserted. For these standard-voltage devices, the polarity of the reset input signal is programmable using PSDsoft (active-high or active-low), to match the functionality of your MCU reset. Note: It is not recommended to drive the reset input of the MCU and the reset input of the PSD with a simple RC circuit between power on ground. The input threshold of the MCU and the PSD devices may differ, causing the devices to enter and exit reset at different times because of slow ramping of the signal. This may result in the PSD not being operational when accessed by the MCU. It is recommended to drive both devices actively. A supervisory device or a gate with hysteresis is recommended. For low-voltage ZPSD211RV devices only, the reset input must be asserted for at least 500 nsec. The ZPSD211RV will not be functional for an additional 500 nsec after reset is de-asserted (see Figure 8). These low voltage ZPSD211RV devices require an active-low polarity signal for reset. Unlike the PSD211R, the polarity of the reset input is not programmable for the ZPSD211RV. If your MCU operates with an active high reset, you must invert this signal before driving the ZPSD211RV reset input. You must design your system to ensure that the PSD comes out of reset and the PSD is active before the MCU makes its first access to PSD memory. Depending on the characteristics and speed of your MCU, a delay between the PSD reset and the MCU reset may be needed.
18
PSD211R Family
12. Control Signals
(Cont.)
Table 8A. External PSD Signal States During and Just After Reset Signal State During Reset
Input (Hi-Z) Input (Hi-Z) PSD211R, ZPSD211R ZPSD211RV MCU I/O Chip Select Outputs, CS0-CS7, CMOS Chip Select Outputs, CS0-CS7, Open Drain PSD211R, ZPSD211R ZPSD211RV PSD211R, ZPSD211R ZPSD211RV PSD211R, ZPSD211R ZPSD211RV Logic 0 Hi-Z Input (Hi-Z Logic 1 Hi-Z Hi-Z Hi-Z Input (Hi-Z) Logic 1 Hi-Z
Signal State Just After Reset
(Note 1) MCU address and/or data Input (Hi-Z) MCU address MCU address Input (Hi-Z) Per CS equations Per CS equations Per CS equations Per CS equations Input (Hi-Z) Per CS equations Per CS equations
Port
AD0/A0AD15/A15 Port Pins PA0-PA7
Configured Mode of Operation
All MCU I/O Latched Address Out
Port Pins PB0-PB7
Address or Logic Inputs, A16-A18 Port Pins PC0-PC2 Chip Select Outputs, CS8-CS10, CMOS
NOTE: 1. Signal is valid immediately after reset for non-V devices. ZPSD211RV devices need an additional 500 nsec after reset before signal is valid.
Table 8B. Internal PSD Signal States During and Just After Reset Internal Signal State During Reset Internal Signal State During Power-Down
Per equations for each internal signal
Component
PAD A and PAD B
Internal Signal
CS0-CS10 CSIOPORT, ES0-ES7 N/A
Logic 1 (inactive) Per CS Equations Logic 0 (inactive)
All registers in CSIOPORT address space, including: Direction Data PMR (turbo bit, ZPSD only)
NOTE: N/A = Not Applicable
Logic 0 in all bit of Logic 0 until all registers changed by MCU
Figure 8. The Required Reset Cycle for ZPSD211RV Devices Only.
VIH VIL 500 ns RESET LOW 500 ns RESET HIGH ZPSD211R(V) IS OPERATIONAL
19
PSD211R Family
13.0 Program/Data Space and the 8031
This section only applies to users who have an 8031 or compatible MCU that outputs a signal such as PSEN when accessing program space. If this applies to you, be aware of the following: the PSD211R can be configured using PSDsoft such that the EPROM is either 1) accessed by PSEN only (Figure 10); or 2) accessed by PSEN or RD (Figure 9). The default is PSEN only unless changed in PSDsoft.
Figure 9. Combined Address Space
ADDRESS
PAD
INTERNAL RD
PSEN
OE EPROM CS CS OE I/O PORTS
Figure 10. 8031-Compatible Separate Code and Data Address Spaces
I/O PORTS OE INTERNAL RD CS
ADDRESS
PAD
CS EPROM PSEN OE
20
PSD211R Family
14.0 System Applications
In Figure 11, the PSD211R is configured to interface with Intel's 80C31, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 80C31 uses signals RD to read from data memory and PSEN to read from code memory. It uses WR to write into the data memory. It also uses active high reset and ALE signals. Only the necessary connections are shown.
Figure 11. Interface With Intel's 80C31
VCC
MICROCONTROLLER
31 19 EA/VP X1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 1 13 3 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7
0.1F 44 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 A19/CSI GND 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43
18
X2
9
RESET
12 13 14 15 1 2 3 4 5 6 7 8
INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 RD WR/VPP PSEN ALE RESET
Reset
80C31
PSD211R
34
12
NOTE: RESET to the PSD211R must be the output of a RESET chip or buffer. If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the PSD211R (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
21
PSD211R Family
14.0 System Applications
(cont.)
In Figure 12, the PSD211R is configured to interface with Motorola's 68HC11, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 68HC11 uses E and R/W signals to derive the read and write strobes. It uses the term AS (address strobe) for the address latch pulse. RESET is an active low signal. Only the necessary connections are shown.
Figure 12. Interface With Motorola's 68HC11
VCC
MICROCONTROLLER
20 21 22 23 24 25 43 45 47 49 44 46 48 50 34 33 32 31 30 29 28 27 52 51 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 E R/W AS RESET XIRQ IRQ MODB MODA XTAL EXTAL 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 5 6 4 17 18 19 2 3 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 13 3 1
0.1F 44 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 E R/W/VPP AS RESET PSEN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 A19/CSI 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43
PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PE3 PD4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VRH VRL
VCC GND
PSD211R
34
12
68HC11 Reset
22
PSD211R Family
15.0 Security Mode
Security Mode in the PSD211R locks the contents of PAD A, PAD B, and all the configuration bits. The EPROM and I/O contents can be accessed only through the PAD. The Security Mode must be set by PSDsoft prior to run-time. The Security Bit can only be erased on the UV parts using a full-chip erase. If Security Mode is enabled, the contents of the PSD211R can not be uploaded (copied) on a device programmer.
16.0 Power Management
PSDs from all 211R families use zero-power memory techniques that place memory into Standby Mode between MCU accesses. The memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to Standby. This is done automatically and the designer has to do nothing special to benefit from this feature. In addition to the benefits of Zero-power memory technology, there are ways to gain additional savings. The following factors determine how much current the entire PSD device uses: * Use of CSI (Chip Select Input) * Setting of the CMiser bit * Setting of the Turbo Bit (ZPSD only) * The number of product terms used in the PAD * The composite frequency of the input signals to the PAD * The loading on I/O pins. The total current consumption for the PSD is calculated by summing the currents from memory, PAD logic, and I/O pins, based on your design parameters and the power management options used.
16.1 CSI Input
Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire PSD to enter Power-down Mode, independent of any transition on the MCU bus (address and control) or other PSD inputs. During this time, the PSD device draws only standby current (micro-amps). Alternately, driving a logic 0 on the CSI pin returns the PSD to normal operation. See Tables 7A and 7B for information on signal states during Power-down Mode. The CSI pin feature is available only if enabled in the PSDsoft Configuration utility.
16.2 CMiser bit
In addition to power savings resulting from the Zero-power technology used in the memory, the CMiser feature saves even more power under certain conditions. Savings are significant when the PSD is configured for an 8-bit data path because the CMiser feature turns off half of the array when memory is being accessed (the memory is divided internally into odd and even arrays). See the DC characteristics table for current usage related to the CMiser bit. You should keep the following in mind when using this bit: * Setting of this bit is accomplished with PSDsoft at the design stage, prior to run-time. * Memory access times are extended by 10 nsec for standard voltage (non-V) devices, and 20 nsec for low voltage (V) devices.
23
PSD211R Family
16. Power Management
(cont.)
16.3 Turbo Bit (ZPSD only)
The turbo bit is controlled by the MCU at run-time and is accessed through bit zero of the Power Management Register (PMR). The PMR is located in CSIOPORT space at offset 10h.
Power Management Register (PMR)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Turbo bit 1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*
1= OFF
*Future Configuration bits are reserved and should be set to one when writing to this register. The default value at reset of all bits in the PMR is logic 0, which means the Turbo feature is enabled. The PAD logic (PAD A and PAD B) of the PSD will operate at full speed and full power. When the Turbo bit is set to logic 1, the Turbo feature is disabled. When disabled, the PAD logic will draw only standby current (micro-amps) while no PAD inputs change. Whenever there is a transition on any PAD input (including MCU address and control signals), the PAD logic will power up and will generate new outputs, latch those outputs, then go back to Standby Mode. Keep in mind that the signal propagation delay through the PAD logic increases by 10 nsec for non-V devices, and 20 nsec for V devices while in non-turbo mode. Use of the Turbo bit does not affect the operation or power consumption of memory. Tremendous power savings are possible by setting the Turbo bit and going into non-turbo mode. This essentially reduces the DC power consumption of the PAD logic to zero. It also reduces the AC power consumption of PAD logic when the composite frequency of all PAD inputs change at a rate less than 40 MHz for non-V devices, and less than 20 MHz for V devices. Use figures 13 and 14 to calculate AC and DC current usage in the PAD with the Turbo bit on and off. You will need to know the number of product terms that are used in your design and you will have to calculate the composite frequency of all signals entering the PAD logic.
16.4 Number of Product Terms in the PAD Logic
The number of product terms used in your design relates directly to how much current the PADs will draw. Therefore, minimizing this number will be in your best interest if power is a concern for you. Basically, the amount of product terms your design will use is based on the following (see Figure 4): * Each of the EPROM block selects, ES0-ES7 uses one product term (for a total of 8). * The CSIOPORT select uses one product term. * Port B, pins PB0-PB3 are allocated four product terms each if used as outputs. * Port B, pins PB4-PB7 are allocated two product terms each if used as outputs. * Port C, pins PC0-PC2 are allocated one product term each if used as outputs. Given the above product term allocation, keep the following three points in mind when calculating the total number of product terms your design will require: 1) The EPROM block selects and CSIOPORT select will use a product term whether you use these blocks or not. This means you start out with 9 product terms, and go up from there. 2) For Port B, if you use a pin as an output and your logic equation requires only one product term, you still have to include all the available product terms for that pin for power consumption, even though only one product term is specified. For example, if the output equation for pin PB0 uses just one product term, you will have to count PB0 as contributing four product terms to the overall count. With this in mind, you should use Port C for the outputs that only require one product term and PB4-7 for outputs that require two product terms. Use pins PB0-3 if you need outputs requiring more than two product terms or you have run out of outputs. 3) The following PSD functions do not consume product terms: MCU I/O mode, Latched Address Output, and PAD inputs (logic or address).
24
PSD211R Family
16.0 Power Management
(cont.)
16.5 Composite Frequency of the Input Signals to the PAD Logic
The composite frequency of the input signals to the PADs is calculated by considering all transitions on any PAD input signal (including the MCU address and control inputs). Once you have calculated the composite frequency and know the number of product terms used, you can determine the total AC current consumption of the PAD by using Figure 13 or Figure 14. From the figures, notice that the DC component (f = 0 MHz) of PAD current is essentially zero when the turbo feature is disabled, and that the AC component increases as frequency increases. When the turbo feature is disabled, the PAD logic can achieve low power consumption by becoming active briefly, only when inputs change. For standard voltage (non-V) devices, the PAD logic will stay active for 25 nsec after it detects a transition on any input. If there are more transitions on any PAD input within the 25 nsec period, these transitions will not add to power consumption because the PAD logic is already active. This effect helps reduce the overall composite frequency value. In other words, narrowly spaced groups of transitions on input signals may count as just one transition when estimating the composite frequency. Note that the "knee" frequency in Figure 13 is 40 MHz, which means that the PAD will consume less power only if the composite frequency of all PAD inputs is less than 40 MHz. When the composite frequency is above 40 MHz, the PAD logic never gets a chance to shut down (inputs are spaced less than 25 nsec) and no power savings can be achieved. Figure 14 is for low-voltage devices in which the "knee" frequency is 20 MHz. Take the following steps to calculate the composite frequency: 1) Determine your highest frequency input for either PAD A or PAD B. 2) Calculate the period of this input and use this period as a basis for determining the composite frequency. 3) Examine the remaining PAD input signals within this base period to determine the number of distinct transitions. 4) Signal transitions that are spaced further than 25 nsec apart count as a distinct transition (50 nsec for low-voltage V devices). Signal transitions spaced closer than 25 nsec count as the same transition. 5) Count up the number of distinct transitions and divide that into the value of the base period. 6) The result is the period of the composite frequency. Divide into one to get the composite frequency value. Unfortunately, this procedure is complicated and usually not deterministic since different inputs may be changing in various cycles. Therefore, we recommend you think of the situation that has the most activity on the inputs to the PLD and use this to calculate the composite frequency. Then you will have a number that represents your best estimate at the worst case scenario. Since this is a complicated process, the following example should help.
Example Composite Frequency Calculation
Suppose you had the following circuit:
80C31 (12 MHz Crystal)
AD0-AD7 A8-A16 ALE RD WR PSEN CSI
ZPSD211R PA PB PC
Latched Address Output (LA0-LA7) 3 Inputs: Int, Sel, Rdy 6 MCU I/O Outputs 3 Chip-Select Outputs
25
PSD211R Family
16.0 Power Management
(cont.)
All the inputs shown, except CSI, go to the PAD logic. These signals must be taken into consideration when calculating the composite frequency. Before we make the calculation, let's establish the following conditions: * The input with the highest frequency is ALE, which is 2 MHz. So our base period is 500 nsec for this example. * Only the address information from the multiplexed signals AD0-AD7 reach the PAD logic because of the internal address latch. Signal transitions from data on AD0-AD7 do not reach the PADs. * The three inputs (Int, Sel, or Rdy) change state very infrequently relative to the 80C31 bus signals. Now, lets assume the following is a snapshot in time of all the input signals during a typical 80C31 bus cycle. We'll use a code fetch as an example since that happens most often.
ONE TYPICAL 80C31 BUS CYCLE (2 MHz, 500 nsec)
ALE PSEN 1 AD0-AD7 A8-A15 INT SEL RDY 3 ADDR 2 DATA
< 25 nsec
FOUR DISTINCT TRANSITIONS
The calculation of the composite frequency is as follows:
* There are four distinct transitions (first four dotted lines) within the base period of
500 nsec. These first four transitions all count toward the final composite frequency.
* The transition at (1) in the diagram does not count as a distinct transition because it is
within 25 nsec of a neighboring transition (use 50 nsec for a ZPSD211RV device). * Transition (2) above does not add to the composite frequency because only the internally latched address signals reach the PADs, the data signal transitions do not. * The transition at (3) just happens to appear in this snapshot, but its frequency is so low that it is not a significant contributor to the overall composite frequency, and will not be used. * Divide the 500 nsec base period by the four (distinct transitions), yielding 125 nsec. 1/125 nsec = 8 MHz. * Use 8 MHz as the composite frequency of PAD inputs when calculating current consumption. (See the next section for a sample current calculation.)
16.6 Loading on I/O pins
A final consideration when calculating the current usage for the entire PSD device is the loading on I/O pins. All specifications for PSD current consumption in this document assume zero current flowing through PSD I/O pins (including ADIO). I/O current is dictated by the individual design implementation, and must be calculated by the designer. Be aware that I/O current is a function of loading on the pins and the frequency at which the signals toggle.
26
PSD211R Family
17.0 Calculating Power
Once you have read the "Power Management" section, you should be able to calculate power. The following is a sample power calculation:
Conditions
Part Used MCU ALE Clock Frequency Composite ZPLD input Frequency % EPROM Access % I/O access % Time CSI is high (standby mode) % Time CSI is low (normal operation mode) # Product terms used (see previous section) Turbo bit CMiser bit MCU Bus Configuration = = = = = = = = = = = ZPSD211R (VCC = 5.0 V) 2.0 MHz 8.0 MHz (see example in above section) 80% 20% 90% 10% 10 OFF (Turbo Mode disabled) ON 8-bit multiplexed bus mode
Calculation (Based on Typical AC and DC Currents)
ICC total = Istandby x % time CSI is high + [ICC (AC) + ICC (DC)] x % time CSI is low. = Istandby x % time CSI is high + [%EPROM Access x 0.8 mA/MHz x Freq. ALE + ZPLD AC current (Figure 13: 10 PTs, 8 MHz, Non-Turbo)] x % time CSI is low. = 10 A x 0.9 + (0.8 x 0.8 mA/MHz x 2 MHz + 5.0 mA) x 0.1 = 9.0 A + (1.28 mA + 5.0 mA) x 0.1 = 637 A, based on the system operating in standby 90% of the time
NOTES: 1. 2. 3. 4. 5. Calculation is based on the assumption that Iout = 0 mA (no I/O pin loading). ICC (DC) is zero for all ZPSD devices operating in non-turbo mode. 10 product terms: 8 for EPROM, 1 for CSIOPORT, 1 for CS8 The 5% I/O access in the conditions section is when the MCU accesses CSIOPORT space. Standby Mode can also be achieved without using the CSI pin. The ZPSD device will automatically go into Standby while no inputs are changing on any pin, and Turbo Mode is disabled.
27
PSD211R Family
17.0 Calculating Power
(cont.)
Figure 13. Typical ICC vs. Frequency for the PAD (VCC = 5 V)
45 40 35 30 ICC (mA) 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 Composite Frequency at PAD Inputs (MHz)
36 PT Turbo 36 PT Non-Turbo 10 PT Turbo 10 PT Non-Turbo
Figure 14. Typical ICC vs. Frequency for the PAD (VCC = 3 V)
14 12 10 ICC (mA) 8 6 4 2 0 0 5 10 15 20 25 Composite Frequency at PAD Inputs (MHz)
36 PT Turbo 36 PT Non-Turbo 10 PT Turbo 10 PT Non-Turbo
28
PSD211R Family
Figure 15. IOL vs. VOL (5 V 10%) ZPSD211R(V)
40
Figure 16. Normalized ICC (DC vs. VCC ) (VCC = 3.0 V) ZPSD211R(V)
35
3.5 3.0 2.5 ICC
Temp. = 125C Temp. = 25C
30
25 IOL (mA)
20
2.0 1.5 1.0 0.5 2.5 3.0 2.7 3.5 4.0 4.5 (V) VCC 5.0 5.5 6.0
15
10
5
0 0.00 0.10 0.20 0.30 0.40 VOL (V) 0.50 0.60 0.70 0.80
Figure 17. Normalized ICC (AC) (VCC = 3.0 V) ZPSD211R(V)
Figure 18. Normalized Access Time (T6) (VCC = 3.0 V) ZPSD211R(V)
2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 2.5 3.0 2.7 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0 ACCESS TIME
1.1 1.05 1.0 0.95 0.9 0.85 0.8 0.75 0.7 0.65 2.5 3.0 2.7 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0
ICC (AC)
29
PSD211R Family
18.0 Specifications
18.1 Absolute Maximum Ratings 1 Symbol
TSTG
Parameter
Storage Temperature Voltage on any Pin
Condition
CERDIP PLASTIC With Respect to GND With Respect to GND With Respect to GND
Min
- 65 - 65 - 0.6 - 0.6 - 0.6
Max
+ 150 + 125 +7 + 14 +7
Unit
C C V V V V
VPP VCC
Programming Supply Voltage Supply Voltage ESD Protection
>2000
NOTE:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
18.2 Operating Range Range
Commercial Industrial
Temperature
0 C to +70C -40 C to +85C
VCC
+ 3 V1, + 5 V +3V ,+5V
1
VCC Tolerance
10% 10%
NOTE: 1. 3 V available on ZPSD211RV only.
18.3 Recommended Operating Conditions Symbol
VCC VCC
Parameter
Supply Voltage Supply Voltage
Conditions
PSD Versions, All Speeds ZPSD V Versions Only, All Speeds
Min
4.5 2.7
Typ Max Unit
5 3.0 5.5 5.5 V V
18.4 Pin Capacitance 1 Symbol
CIN COUT CVPP
Parameter
Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for WR/VPP or R/W/VPP)
Conditions
VIN = 0 V VOUT = 0 V VPP = 0 V
Typical 2 Max Unit
4 8 18 6 12 25 pF pF pF
NOTES: 1. This parameter is only sampled and is not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages.
30
PSD211R Family
18.5 AC/DC Characteristics - PSD211R/ZPSD211R (All 5 V devices)
Symbol
VCC VIH VIL VOH
Parameter
Supply Voltage High-Level Input Voltage Low-Level Input Voltage Output High Voltage Output Low Voltage (See Figure 14) ZPSD211R Standby Supply Current Standby Supply Current All Speeds
Conditions
Min
4.5 2 - 0.5 4.4 2.4
Typ
5
Max
5.5 VCC + .1 0.8
Unit
V V V V V
4.5 V < VCC > 5.5 V 4.5 V < VCC > 5.5 V IOH = - 20 A, VCC = 4.5 V IOH = - 2 mA, VCC = 4.5 V IOL = 20 A, VCC = 4.5 V IOL = 8 mA, VCC = 4.5 V
4.49 3.9 0.01 0.15 10 50 0.1 0.45 20 100 1 10
V V A A A A A
VOL
ISB
(Notes 1,4) PSD211R
ILI ILO
Input Leakage Current Output Leakage Current
VSS < VIN > VCC .45 < VIN > VCC ZPLD Turbo Mode = Off, f = 0 MHz
-1 -10
.1 5
See ISB 0.5 0 0 0.5 0 0 Fig. 13 0.8 1.8 1 0 0 1 0 0 1 2.0 4.0
ZPSD211R Operating Suppy Current ICC (DC) (Note 3) PSD211R Operating Supply Current ZPLD AC Base ICC (AC) (Note 3) EPROM Access AC Adder
NOTES: 1. 2. 3. 4.
ZPLD Turbo Mode = On, f = 0 MHz EPROM, f = 0 MHz SRAM, f = 0 MHz PLD, f = 0 MHz EPROM, f = 0 MHz SRAM, f = 0 MHz (See Figure 13) CMiser = On and 8-Bit Bus Mode CMiser = Off
mA/PT A A mA/PT A A mA/MHz mA/MHz mA/MHz
CMOS inputs: GND 0.3 V or VCC 0.3V. TTL inputs: VIL 0.8 V, VIH 2.0 V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode.
31
PSD211R Family
18.6 AC/DC DC Characteristics ZPSD211RV (3 V devices only)
Symbol
VCC VIH VIL VOH
Parameter
Supply Voltage High-Level Input Voltage Low-Level Input Voltage Output High Voltage
Conditions
All Speeds 2.7 V < VCC > 5.5 V 2.7 V < VCC > 5.5 V IOH = - 20 A, VCC = 2.7 V IOH = - 1 mA, VCC = 2.7 V IOL = 20 A, VCC = 2.7 V IOL = 4 mA, VCC = 2.7 V VCC = 3.0 V VIN = VCC or GND VOUT = VCC or GND ZPLD Turbo Mode= Off, f = 0 MHz, VCC = 3.0 V
Min
2.7 .7 VCC - 0.5 2.6 2.3
Typ
3
Max
5.5 VCC + .5 .3 VCC
Unit
V V V V V
2.69 2.4 0.01 0.15 1 0.1 0.45 5 1 1
V V A A A A
VOL ISB
(Notes 1,4)
Output Low Voltage Standby Supply Current Input Leakage Current Output Leakage Current
ILI ILO
-1 -1
.1 .1 See ISB 0.17 0 Fig. 14 0.4 0.9
ICC (DC)
(Note 3)
Operating Supply Current
ZPLD Turbo Mode= On, f = 0 MHz, VCC = 3.0 V EPROM, f = 0 MHz, VCC = 3.0 V
0.35 0 0.5 1 1.7
mA/PT A mA/MHz mA/MHz mA/MHz
ZPLD AC Base ICC (AC)
(Note 3)
See Figure 14 (VCC = 3.0 V) CMiser = On and 8-Bit Bus Mode (VCC = 3.0 V) CMiser = Off (VCC = 3.0 V)
EPROM Access AC Adder
NOTES: 1. 2. 3. 4.
CMOS inputs: GND 0.3 V or VCC 0.3V. TTL inputs: VIL 0.8 V, VIH 2.0 V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode.
32
PSD211R Family
18.7 Timing Parameters - PSD211R/ZPSD211R (All 5 V devices)
Symbol
T1 T2 T3 T4 T5 T6 T7 T8 T8A T9 T10 T11 T12 T12A T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T30 T31 T32 T33 T34 T35 T36
NOTES: 1. 2. 3.
Parameter
ALE or AS Pulse Width Address Set-up Time Address Hold Time Leading Edge of Read to Data Active ALE Valid to Data Valid Address Valid to Data Valid CSI Active to Data Valid Leading Edge of Read to Data Valid Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode Read Data Hold Time Trailing Edge of Read to Data High-Z Trailing Edge of ALE or AS to Leading Edge of Write RD, E, PSEN Pulse Width WR Pulse Width Trailing Edge of Write or Read to Leading Edge of ALE or AS Address Valid to Trailing Edge of Write CSI Active to Trailing Edge of Write Write Data Set-up Time Write Data Hold Time Port to Data Out Valid Propagation Delay Port Input Hold Time Trailing Edge of Write to Port Output Valid ADi1 or Control to CSOi2 Valid ADi1 or Control to CSOi2 Invalid Latched Address Outputs, Port A CSI Active to CSOi2 Active CSI Inactive to CSOi2 Inactive Direct PAD Input 3 as Hold Time R/W Active to E High E End to R/W AS Inactive to E high Address to Leading Edge of Write
CMiser On = Unit Min Max Min Max Min Max Add
18 5 7 0 80 70 80 20 32 0 20 0 35 18 5 70 80 18 5 25 0 30 6 5 8 8 0 18 18 0 18 20 20 22 37 37 9 9 0 20 20 0 20 6 5 0 35 25 25 22 40 40 9 9 12 30 30 0 25 6 4 0 45 25 5 120 130 25 5 28 0 50 35 35 28 50 50 0 35 0 60 35 5 150 160 30 10 35 20 5 8 0 100 90 100 32 32 0 35 40 12 10 0 160 150 160 55 55 0 0 0 0 10 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 10 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-70
-90
-15
ADi = any address line. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E, WR or R/W, transparent PC0-PC2, ALE (or AS). 4. Control signals RD/E or WR or R/W.
33
PSD211R Family
18.8 Timing Parameters - ZPSD211RV (3 V devices only)
-20
Symbol
T1 T2 T3 T4 T5 T6 T7 T8 T8A T9 T10 T11 T12 T12A T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
-25
Min
60 20 20 0
Parameter
ALE or AS Pulse Width Address Set-up Time Address Hold Time Leading Edge of Read to Data Active ALE Valid to Data Valid Address Valid to Data Valid CSI Active to Data Valid Leading Edge of Read to Data Valid Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode Read Data Hold Time Trailing Edge of Read to Data High-Z Trailing Edge of ALE or AS to Leading Edge of Write RD, E, PSEN, or DS Pulse Width WR Pulse Width Trailing Edge of Write or Read to Leading Edge of ALE or AS Address Valid to Trailing Edge of Write CSI Active to Trailing Edge of Write Write Data Set-up Time Write Data Hold Time Port to Data Out Valid Propagation Delay Port Input Hold Time Trailing Edge of Write to Port Output Valid ADi1 or Control to CSOi2 Valid ADi1 or Control to CSOi2 Invalid
Min
50 15 15 0
Max
Max
CMiser Turbo On = Off = Add Add
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 0
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
200 200 200 50 70 0 50 0 75 45 5 200 200 40 12 50 0 60 5 4 55 55 60 5 4 0 0 85 55 5 250 250 50 15 0
250 250 250 60 80
20 20 20 0 0 0
55
0 0 0 0 0 0 0 0 0
60
0 0
70 60 60 60
0 0 0 0
Latched Address Outputs, Port A
34
PSD211R Family
18.8 Timing Parameters - ZPSD211RV (3 V devices only) (cont.)
-20
Symbol
T29 T30 T31 T32 T33 T34 T35 T36
-25
Min
3 80 80 9 9 0 50 50 0 40 90 90
Parameter
Hold Time of Port A Valid During Write CSOi Trailing Edge CSI Active to CSOi2 Active CSI Inactive to CSOi2 Inactive Direct PAD Input 3 as Hold Time R/W Active to E or DS Start E or DS End to R/W AS Inactive to E high Address to Leading Edge of Write
Min
3 9 9 0 40 40 0 35
Max
Max
CMiser Turbo On = Off = Add Add
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Unit
ns ns ns ns ns ns ns ns
NOTES: 1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E, WR or R/W, transparent PC0-PC2, ALE (or AS). 4. Control signals RD/E or WR or R/W.
35
PSD211R Family
18.9 Timing Diagrams for all PSD211R Parts
Figure 19. Timing using RD and WR signals
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 Active High ALE Active Low ALE ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 1 11 4 8 12 RD/E as RD 5 PSEN 12A WR/VPP or RW as WR Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A 13 36 13 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32
18
INPUT
19
20 OUTPUT
INPUT 23 ADDRESS B
OUTPUT
See referenced notes on page 38.
36
PSD211R Family
Figure 20. Timing Using R/W and E signals
READ CYCLE 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 32 STABLE INPUT 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 Active High AS Active Low AS ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 1 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32
35 4 13
35 33 34 12 36 33 12 13
RD/E as E 5
8
34
WR/VPP or R/W as R/W 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A INPUT 19 20 OUTPUT
INPUT 23 ADDRESS B
OUTPUT
See referenced notes on page 38.
37
PSD211R Family
Figure 21. Chip-select Output Timing
30 A19/CSI as CSI Direct PAD (1) Input Multiplexed (2) PAD Inputs 2 ALE 1 3
31
INPUT STABLE
or ALE 21 CSOi (3, 4) 22
Notes for Timing Diagrams
1. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E, WR or R/W, transparent PC0-PC2, ALE in non-multiplexed modes. 2. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): A0/AD0-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0-PC2. 3. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). 4. CSOi product terms can include any of the PAD input signals shown in Figure 4, except for reset and CSI.
38
PSD211R Family
18.10. AC Testing
Figure 22A. AC Testing Input/Output Waveform (5 V Versions )
3.0V TEST POINT 0V 1.5V
Figure 22B. AC Testing Input/Output Waveform (3 V Versions )
0.9 VCC TEST POINT 0V 1.5V
Figure 23A. AC Testing Load Circuit (5 V Versions )
2.01 V
195 DEVICE UNDER TEST
CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE)
Figure 23B. AC Testing Load Circuit (3 V Versions )
2.0 V
400 DEVICE UNDER TEST
CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE)
39
PSD211R Family
19.0 Pin Assignments
Pin Assignments
PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC
Pin No. 44-Pin PLDCC/CLDCC (Package Type L/J)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin No. 44-Pin PQFP (Package Type M)
39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
40
PSD211R Family
2 WR/VPP or R/W
43 A19/CSI
3 RESET
20.0 Package Information
6 PB5 5 PB6
1 PSEN
42 PC2
41 PC1
PA3 18
PA2 19
PA1 20
PA0 21
RD/E 22
AD0/A0 23
AD1/A1 24
AD2/A2 25
AD3/A3 26
AD4/A4 27
(TOP VIEW)
Figure 25. Drawing M1 - 44 Pin Plastic Quad Flatpack (PQFP) (Package Type M)
PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9
40 WR/VPP or R/W 39 PSEN
38 VCC 37 A19/CSI
41 RESET
36 PC2
35 PC1
AD5/A5 28
Figure 24. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J)
40 PC0
44 VCC
4 PB7
PB4 PB3 PB2
7 8 9
39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6
PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17
34 PC0
44 PB5
43 PB6
42 PB7
33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6
PA5 10 PA4 11
PA3 12
PA2 13
PA1 14
PA0 15
RD/E 16
AD0/A0 17
AD1/A1 18
AD2/A2 19
AD3/A3 20
AD4/A4 21
(TOP VIEW)
AD5/A5 22
41
PSD211R Family
21.0 Package Drawings
Drawing J2 - 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J)
D D1
3 2 1 44
E1
E
B1
C
B D3 D2
A1 A2 A
e1 E3 E2
Family: Plastic Leaded Chip Carrier
Millimeters Symbol
A A1 A2 B B1 C D D1 D2 D3 E E1 E2 E3 e1 N
Inches Notes Min
0.165 0.100 0.148 0.013 0.026 0.0097 0.685 0.650 0.590 Reference 0.500 0.685 0.650 0.590 Reference Reference 0.500 0.050 44 0.695 0.654 0.630 Reference Reference
030195R6
Min
4.19 2.54 3.76 0.33 0.66 0.246 17.40 16.51 14.99 12.70 17.40 16.51 14.99 12.70 1.27 44
Max
4.57 2.79 3.96 0.53 0.81 0.262 17.65 16.61 16.00 17.65 16.61 16.00
Max
0.180 0.110 0.156 0.021 0.032 0.0103 0.695 0.654 0.630
Notes
Reference
42
PSD211R Family
Drawing L4 - 44-Pin Pocketed Ceramic Leaded Chip Carrier (CLDCC) - CERQUAD (Package Type L)
D D1
3 2 1 44
E1
E
View A
Commercial and Industrial packages include the lead pocket on the underside of the package but Military packages do not.
B1 A2
C
B D3 D2 A1 A
e1 E3 E2
View A
Family: Ceramic Leaded Chip Carrier - CERQUAD
Millimeters Symbol
A A1 A2 B B1 C D D1 D2 D3 E E1 E2 E3 e1 N 17.40 16.31 14.73 12.70 1.27 44
Inches Notes Min
0.155 0.090 0.120 0.017 0.026 0.006 0.685 0.642 0.580 Reference 0.500 0.685 0.642 0.580 Reference Reference 0.500 0.050 44
030195R8
Min
3.94 2.29 3.05 0.43 0.66 0.15 17.40 16.31 14.73 12.70
Max
4.57 2.92 3.68 0.53 0.81 0.25 17.65 16.66 16.26 17.65 16.66 16.26
Max
0.180 0.115 0.145 0.021 0.032 0.010 0.695 0.656 0.640
Notes
Reference 0.695 0.656 0.640 Reference Reference
43
PSD211R Family
Drawing M1 - 44-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
D D1 D3
44
1 2 3
Index Mark E3 E1 E
A1
Standoff: 0.10 mm Min 0.25 mm Max A A2
C a
B
e1
L
Family: Plastic Quad Flatpack (PQFP)
Millimeters Symbol
A A1 A2 B C D D1 D3 E E1 E3 e1 L N 0.73 44 1.95 0.30 0.13 13.20 10.00 8.00 13.20 10.00 8.00 0.80 1.03 Reference Reference 0.029 44
030195R4
Inches Notes Min
0 - Reference 0.042 0.077 0.012 0.005 0.520 0.394 Reference 0.315 0.520 0.394 0.315 0.031 0.040 Reference Reference Reference 0.083 0.018 0.009
Min
0 - 1.075
Max
7 2.35 2.10 0.45 0.23
Max
7 0.092
Notes
Reference
44
22.0
PSD211R Ordering Information
22.1 PSD211R Family - Selector Guide
MCU
ZPSD @ 2.7 V 8-Bit 16-Bit Interface Inputs Product PLD Data Data Terms Outputs Page Reg. Ports Open Drain EPROM
Part #
PLDs/Decoders
I/O
Memory
SRAM
Other
Peripheral Security Mode
PSD @ 5V
ZPSD @ 5V
PSD211R
ZPSD211R
ZPSD211RV
X
STD-M
14
40
11
19
256Kb
X
PSD211R Family
45
PSD211R Family
22.0 PSD211R Ordering Information
(cont.)
22.2 Part Number Construction
Z PSD 413A2 V -A -20 J I Temperature (Blank = Commercial, I = Industrial, M = Military) Package Type Speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) Revision (Blank = No Revision) Supply Voltage (Blank = 5V, V = 3 Volt) Base Part Number - see Selector Guide PSD (WSI Programmable System Device) Fam. Power Down Feature (Blank = Standard, Z = Zero Power Feature)
22.3 Ordering Information Speed (ns)
70 70 70 90 90 150 150 150 70 70 70 90 90 150 150 150 200 200 200 200 250 250
Part Number
PSD211R-B-70J PSD211R-B-70L PSD211R-B-70M PSD211R-B-90J PSD211R-B-90JI PSD211R-B-15J PSD211R-B-15L PSD211R-B-15M ZPSD211R-B-70J ZPSD211R-B-70L ZPSD211R-B-70M ZPSD211R-B-90JI ZPSD211R-B-90MI ZPSD211R-B-15J ZPSD211R-B-15L ZPSD211R-B-15M ZPSD211RV-B-20J ZPSD211RV-B-20JI ZPSD211RV-B-20L ZPSD211RV-B-20M ZPSD211RV-B-25J ZPSD211RV-B-25JI
Package Type
44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PLDCC
Operating Temperature Range
Comm'l Comm'l Comm'l Comm'l Industrial Comm'l Comm'l Comm'l Comm'l Comm'l Comm'l Industrial Industrial Comm'l Comm'l Comm'l Comm'l Industrial Comm'l Comm'l Comm'l Industrial
46
PSD211R, ZPSD211R, ZPSD211RV
REVISION HISTORY Table 1. Document Revision History
Date Jan-1997 Jul-1997 Feb-1998 Rev. 1.0 1.0 1.1 Description of Revision PSD211R: Document written in the WSI format. Initial release ZPSD211R, ZPSD211RV: Document written in the WSI format. Initial release Combined Data Sheets. Updated Specifications PSD211R, ZPSD211R, ZPSD211RV: Low Cost Field Programmable Microcontroller Peripherals Front page, and back two pages, in ST format, added to the PDF file Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft Express
31-Jan-2002
1.2
2/3
PSD211R, ZPSD211R, ZPSD211RV
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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